The present invention relates to the field of electronics and more particularly to an analog-to-digital converter as it may be used in telecommunications applications such as receivers for long-haul optical signal transmission.
Digital optical signals traversing an optical fiber link are subject to distortion and noise which may produce bit errors at the receiver side. At higher transmission rates or longer span lengths, error correction may thus be performed at the receiver side to reduce the error rate of distorted signals. A known method of error correction, the Maximum Likelihood Sequence Estimation (MLSE) reducing errors caused by inter-symbol interference (ISI), uses a Viterbi decoder. Viterbi decoders require analog to digital conversion of received optical signal after signal detection in a photodiode.
Most analog to digital converters (ADC) follow a linear scale, i.e. the scale for a given bit resolution is subdivided in equidistant steps per bit. A linear ADC is also the best choice for correcting a noisy input signal with a signal independent noise characteristic like additive white Gaussian noise. Optical noise, however, is signal dependent and therefore the optimum characteristic of the analog-to-digital converter (ADC) is no more linear. It would thus be preferable to use a ADC that follows a non-linear scale in Viterbi decoders for optical applications.
U.S. Pat. No. 6,417,965 discloses an optical amplifier control system that uses a non-linear analog-to-digital converter with a logarithmic scale but does not show an implementation of such an ADC.
It would be possible to implement a parallel ADC with a non-linear characteristic, because the thresholds of the comparators in the parallel ADC would be individually adjustable and could thus be adjusted according to a non-linear scale. The complexity of parallel ADC, however, grows with the square of the bit resolution n of the ADC (i.e., with 2n−1). The complexity of a ADC with a resolution of 4 bit or more is therefore too high to allow a cost effective implementation. Moreover, parallel ADCs have a relatively high input capacity so that they are not well suited for high-frequency applications of 2 GHz or above.
It is thus an object of the present invention to provide an analog-to-digital converter that follows a non-linear scale and that has a lower complexity and allows operation at frequencies of 2 GHz and more.